ADSP-214xx SHARC Processor Hardware Reference 13-23
Sony/Philips Digital Interface
(
DIR_CLK_O), the serial frame sync (DIR_FS_O), and the serial data
(DIR_DAT_O). The high frequency clock (DIR_TDMCLK_O) derived
from the encoded stream is also available if the system requires it.
2. Initialize the DIRCTL register to enable the data decoding. Note that
this peripheral is enabled by default.
Interrupted Data Streams on the Receiver
When using the S/PDIF receiver with data streams that are likely to be
interrupted, (in other words unplugged and reconnected), it is necessary
to take some extra steps to ensure that the S/PDIF receiver’s digital PLL
will re lock to the stream. The steps to accomplish this are described
below.
1. Set up interrupts within the DAI so that the S/PDIF receiver can
generate an interrupt when the stream is reconnected.
2. Within the interrupt service routine (ISR), stop and restart the dig-
ital PLL. This is accomplished by setting and then clearing bit 7 of
the S/PDIF receiver control register.
3. Return from the ISR and continue normal operation.
This method of resetting the digital PLL has been shown to provide
extremely reliable performance when S/PDIF inputs that are interrupted
or unplugged momentarily occur.
The following procedure and the example code show how to reset the dig-
ital PLL. Note that all of the S/PDIF receiver interrupts are handled
through the DAI interrupt controller.
1. Initialize the No Stream Interrupt
/* Enable interrupts (globally) */
BIT SET MODE1 IRPTEN;
/* unmask DAI Hi=Priority Interrupt */
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