Programming Model
13-24 ADSP-214xx SHARC Processor Hardware Reference
bit set imask DAIHI;
ustat1 = DIR_NOSTREAM_INT;
/* Enable no-stream Interrupt on Falling Edge. Interrupt
occurs when the stream is reconnected */
dm(DAI_IRPTL_FE) = ustat1;
/* Enable Hi-priority DAI interrupt */
dm(DAI_IRPTL_PRI) = ustat1;
/* If more than 1 DAI interrupt is being used, it is neces-
sary to determine which interrupt occurred here */
/* Interrupt Service Routine for the DAI Hi-Priority Inter-
rupt. This ISR triggered when the DIR sets no_stream bit */
_DAIisrH:
2. Reset the Digital PLL Inside of the ISR
r8=dm(DAI_IRPTL_H); /* Reading DAI_IRPTL_H
clears interrupt */
ustat2=dm(DIRCTL);
bit set ustat2 DIR_PLLDIS; /* bit_7 disables Dpll only */
dm(DIRCTL)=ustat2;
bit clr ustat2 DIR_PLLDIS; /*reenable the digital pll */
dm(DIRCTL)=ustat2;
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