DDR2 DRAM Controller (ADSP-2146x)
3-58 ADSP-214xx SHARC Processor Hardware Reference
mode programs need to consider if this occurs during a read or write. If
exiting during a read, additional latency occurs because the on-chip DLL
needs to be locked again.
When an internal access occurs (or with careful software control) the
SREF_EXIT bit is set in DDR2CTL0 register and the controller:
1. Exits DDR2 from self-refresh mode by asserting DDR2CKE pin high
2. Waits to meet the t
XSNR
specification (t
XSNR
= t
RAS
+ t
RP
)
3. Issues an auto-refresh command
After the auto-refresh command, the controller waits for the t
RFC
specification to be met before executing the activate command for
the transfer that caused the DDR2 to exit self-refresh mode. For
example:
ustat1 = dm(DDR2CTL0);
bit clr ustat1 DIS_DDR2CTL;
dm(DDR2CTL0) = ustat1; /* release clock */
nop;
ustat2 = dm(DDR2STAT0);
bit tst ustat2 DDR2SRA;
if not TF jump (pc,–2); /* test self-refresh */
dm(DDR2_ADDR) = r0; /* exit self-refresh */
4. For reads, the t
XSRD
time must be satisfied. When exiting self
refresh, ODT must remain low until t
XSRD
is satisfied.
Precharge Power-Down Entry
The DDR2 controller supports DDR2 precharge power down mode. In
this mode, the DDR2 device’s DLL is frozen to maximize power
consumption.
When the DIS_DDR2CKE bit is set to 1 and the DDR2 controller enters an
idle state, it issues a pre-charge command (if necessary) and then, after
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