ADSP-214xx SHARC Processor Hardware Reference 14-7
Precision Clock Generator
can theoretically run at up to the
PCLK frequency. However the DAI/DPI
pin buffers limit the speed to PCLK/4.
Note that the clock output is always set (as closely as possible) to a 50%
duty cycle. If the clock divisor is even, the duty cycle of the clock output is
exactly 50%. If the clock divisor is odd, then the duty cycle is slightly less
than 50%. The low period of the output clock is one input clock period
more than the high period of the output clock. For higher values of an
odd divisor, the duty cycle is close to 50%.
A PCG clock output cannot be fed to its own input.
Frame Sync
The following sections describe the use of frame syncs in the PCGs.
Frame Sync Output
Each of the four units (A through D) also produces a synchronization sig-
nal for framing serial data. The frame sync outputs are much more flexible
since they need to accommodate the wide variety of serial protocols used
by peripherals.
Frame sync generation from a unit is independently enabled and con-
trolled. Sources for the frame sync generation can be either from the
crystal buffer output,
PCLK, or an external pin source. There is only one
external source pin for both frame sync and clock output for a unit.
If an external source is selected for both frame sync and clock output for a
unit, then they operate on the same input signal. Apart from enable and
source select control bits, frame sync generation is controlled by a 20-bit
divisor.
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