ADSP-214xx SHARC Processor Hardware Reference 20-13
UART Port Controller
register. Reading the
UARTRBR register when it is not full returns the previ-
ously received value. When the UARTRBR register is not read in time, newly
received data overwrites the UARTRBR register and the overrun (UARTOE) flag
is set.
With interrupts disabled, these status flags can be polled to determine
when data is ready to move. Note that because polling can be proces-
sor-intensive, it is not typically used in real-time signal processing
environments.
DMA Transfers
The UART interface support both standard and chained DMA. However,
unlike the serial ports, programs cannot insert a TCB in an active chain
using the UART.
In the UART, separate receive and transmit DMA channels move data
between the UART and memory. The software does not have to move
data, it just has to set up the appropriate transfers either through normal
DMA or DMA chaining. Software can write up to two words into the
UARTTHR register before enabling the UART clock. As soon as the UART
DMA engine is enabled, those two words are sent. See also “Functional
Description” on page 2-22.
To perform DMA transfers, the UART has a special set of receive and
transmit registers. These registers are listed in “Standard DMA Parameter
Registers” on page 2-4.
No additional buffering is provided in the UART DMA channel, so the
latency requirements are the same as core transfers. However, the latency
is determined by the bus activity and arbitration mechanism and not by
the processor loading and interrupt priorities.
DMA through the UART is started by setting up values in the DMA
parameter registers and then writing to the transmit and receive control
registers, enabling the module using the UARTEN bits (in the UARTTXCTL and
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