Electrical Specifications
21-26 ADSP-214xx SHARC Processor Hardware Reference
The tasks performed at each interrupt are:
•
TWIRXINT interrupt
This interrupt is generated due to the arrival of one or two data
bytes into the receive FIFO. The TWIRSTART bit should be set at this
time (or earlier) and MDIR should be cleared to reflect the change in
direction of the next transfer. The TWIMDIR bit must be cleared
before the addressing phase of the subsequent transfer begins.
• TWIMCOMP interrupt
This interrupt has occurred due to the completion of the data
receive transfer. At this time the data transmit transfer begins. The
TWIDCNT field should be set to reflect the number of bytes to be
transmitted. Clear the TWIRSTART bit if this is the last transfer.
• TWITXINT interrupt
This interrupt is generated when there is one or two bytes of empty
space in the FIFO. Simple data handling is all that is required.
• TWIMCOM interrupt
The transfer is complete.
Electrical Specifications
All logic complies with the electrical specification outlined in the Philips
I
2
C Bus Specification version 2.1 dated January, 2000.
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