ADSP-214xx SHARC Processor Hardware Reference 4-13
Link Ports—ADSP-2146x
The following is a list of the areas of concern when a program implements
a software protocol scheme for token passing:
• The program must make sure that both link ports are not enabled
to transmit at the same time. In the event that this occurs, data
may be transmitted and lost due to the fact that neither link port is
driving
LACKx. In the example, the TLRQ status bit is polled to
ensure that the master becomes the slave before the slave becomes
the master, avoiding the two transmitter conflict.
• The program must make sure that the link interrupt selection
matches the application. If a status detection scheme using the sta-
tus bits is to be used, it is important to note the following: If a link
port that is configured to receive is disabled while LACKx is asserted,
there is an RC delay before the external pulldown resistor on LACKx
(if enabled) can pull the value below logic threshold. If the LTRQ
status bit is unmasked (in this instance), then an LSR is latched
and the LSRQ interrupt may be serviced, even though unintended, if
enabled.
• The program must make sure that synchronization is not disrupted
by unrelated influences at critical sections where timing control
loops are used to synchronize parallel code execution. Disabling of
nested interrupts is one technique to control this.
Data Transfer
The link ports are able to transfer data using DMA and core.
Link Buffers
The transmit buffer registers (TXLBx) and receive buffer registers (RXLBx)
buffer the data flow through the link port. The transmit and receive
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