ADSP-214xx SHARC Processor Hardware Reference 6-49
FFT/FIR/IIR Hardware Modules
2. Create the TCBs in internal memory. Each TCB corresponds to a
particular channel.
TCBs hold the
FIRCTL2 register which allows programming the
window size and tap size along with up or down sample enable,
sample rate conversion enable, and the conversion ratio for decima-
tion and interpolation filters.
3. Configure the index, modifier, length entries in the TCBs to point
to the corresponding channels’ data buffer, coefficient buffer, and
output data buffer.
The output index register should always point to the start of the
output buffer. However, the input index register’s value should be
initialized based on the explanation provided in “Coefficients and
Input Buffer Storage” on page 6-35.
4. The core configures the FIRCTL1 register with the number of chan-
nels (one channel), fixed- or floating-point format.
5. Set the enable bit to start accelerator operation in the modes con-
figured (in FIRCTL1 and FIRCTL2 registers) by loading the first
channels’ TCB. Once the first channel window is calculated, the
input and output index registers are written back to internal mem-
ory corresponding to the first channel. Once the write back is
complete the accelerator moves into idle.
Multichannel Processing
Figure 6-8 on page 6-51 shows the diagram for multichannel filtering.
Multiple channels are processed in a time division multiplexed (TDM)
format. After completing all the channels, the accelerator can either repeat
the slots or wait for core intervention.
For multichannel filtering, use the following steps.
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