Register Overview
16-4 ADSP-214xx SHARC Processor Hardware Reference
Register Overview
The following sections provide brief descriptions of the primary registers
used to program the timers. For information on the timer registers, see
“Peripheral Timer Registers” on page A-269.
Status and Control Registers (TMSTAT). The (TMSTAT) register indicates
the status of both timers using a single read. The TMSTAT register also con-
tains timer enable bits. Within TMSTAT, each timer has a pair of sticky
status bits, that require a write one-to-set (TIMxEN) or write one-to-clear
(TIMxDIS) to enable and disable the timer respectively.
Counter Registers (TMxCNT). When disabled, the timer counter retains
its state. When re-enabled, the timer counter is re initialized from the
period/width registers based on configuration and mode. The timer coun-
ter value should not be set directly by the software. It can be set indirectly
by initializing the period or width values in the appropriate mode. The
counter should only be read when the respective timer is disabled. This
prevents erroneous data from being returned.
Period Registers (TMxPRD). When enabled and running, the processor
writes new values to the timer period and pulse width registers. The writes
are buffered and do not update the registers until the end of the current
period (when the timer counter register equals the timer period register).
During the pulse width modulation (PWM_OUT), the period value is
written into the timer period registers. Both period and width register val-
ues must be updated “on the fly” since the period and width (duty cycle)
change simultaneously. To insure the period and width value concurrency,
a 32-bit period buffer and a 32-bit width buffer are used.
During the pulse width and period capture (WDTH_CAP) mode, the
period values are captured at the appropriate time. Since both the period
and width registers are read-only in this mode, the existing 32-bit period
and width buffers are used.
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