ADSP-214xx SHARC Processor Hardware Reference A-57
Registers Reference
Controller Status Register 1 (SDSTAT1)
This register reports the SDRAM bank active/idle status. This register is
shown in Figure A-25 and described in Table A-30.
Figure A-25. SDSTAT1 Register
Table A-30. SDSTAT1 Register Bit Descriptions (RO)
Bit Field Field Name Description
7–0 External Bank 0
Status
External Bank 0 Active/Precharge State.
xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
…
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
15–8 External Bank 1
Status
External Bank 0 Active/Precharge State.
xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
…
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
Bit Field (7–4)
External Bank 2
Status
Bit Field (11–8)
Bit Field (3–0)
Bit Field (15–12)
098 37564 2114 12 11 101315
External Bank 0
Status
External Bank 1
Status
External Bank 3
Status
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