Operating Modes
2-30 ADSP-214xx SHARC Processor Hardware Reference
A DMA sequence ends when one of the following occurs.
• The count register decrements to zero, and the chain pointer regis-
ter is zero.
• Chaining is disabled and the channel’s DMA enable bit transitions
from high to low. If the DMA enable bit goes low (=0) and chain-
ing is enabled, the channel enters chain insertion mode (SPORT
only) and the DMA sequence continues.
Once a program starts a DMA process, the process is influenced by two
external controls—DMA channel priority and DMA chaining.
Operating Modes
This section provides information on IOP operating modes.
The SHARC processor contains two independent 32-bit DMA buses
(Figure 2-2). The IOD0 bus is used for the peripherals to the internal
memory and the IOD1 bus is used for external-to-internal memory
transfers.
The IOD0 bus is the path that the IOP uses to transfer data between
internal memory and the peripherals. When there are two or more periph-
erals with active DMAs in progress, they may all require data to be moved
to or from memory in the same cycle. For example, the SPI port may fill
its buffer just as a SPORT shifts a word into its buffer. To determine
which word is transferred first, the DMA channels for each of the
processor’s I/O ports negotiate channel priority with the I/O processor
using an internal DMA request/grant handshake.
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