Clocking
7-6 ADSP-214xx SHARC Processor Hardware Reference
• PWM status registers (PWMSTATx). Report the phase and mode
status for each PWM group.
The traditional read-modify-write operation to enable/disable a
peripheral is different for the PWMs. For more information, see
“Global Control Register (PWMGCTL)” on page A-67.
Clocking
The fundamental timing clock of the PWM controllers is peripheral clock
(PCLK).
Functional Description
The individual elements shown in Figure 7-1 are described in detail in the
following sections.
Two-Phase PWM Generator
Each PWM group is able to generate complementary signals on two out-
puts in paired mode or each group can provide independent outputs in
non-paired mode.
Switching Frequencies
The 16-bit read/write PWM period registers,
PWMPERIOD3–0, control the
PWM switching frequency.
The PWM generator does not support external synchronization
mode.
The fundamental timing unit of the PWM controller is PCLK. Therefore,
for a 200 MHz peripheral clock, the fundamental time increment is 5 ns.
The value written to the
PWMPERIODx register is effectively the number of
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