ADSP-214xx SHARC Processor Hardware Reference 6-37
FFT/FIR/IIR Hardware Modules
x[n-(K-1)], x[n-(K-2)]....x[n-1], x[n], x[n+1]....x[n+W/L-1]
and the IIFIR should point to x[n-(K-1)].
Operating Modes
The FIR core performs a sum-of-products operation to compute the con-
volution sum. It supports single-rate, decimation, and interpolation
functions.
Single Rate Processing
In a single-rate filter, the output result rate is equal to the input sample
rate. The filter output Y(n) is computed according to following equation
where N is the number of filter coefficients: c(i) i = 0,..., N – 1 are the fil-
ter coefficients and x(n) represents the input time-series.
Single Iteration
Results are computed in single iteration when the soft filter length is less
than or equal to 1024.
Multi-Iteration
Results are computed in multiple iterations when the soft filter length is
greater than 1024 (for example, 2048 TAPs on a 1024 hard filter length).
In this mode, the controller implements two iterations of 1024 TAPs.
Note that if the soft filter length is not a multiple of the hard filter length
the controller does iterate until the soft filter length is satisfied.
Example: 550 taps on a 256 tap filter.
Y(n) c k() xn k–()×
k0=
N1–
=
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