Operating Modes
2-36 ADSP-214xx SHARC Processor Hardware Reference
Chain Insert Mode (SPORTs Only)
It is possible to insert a single SPORT DMA operation or another DMA
chain within an active SPORT DMA chain. Programs may need to per-
form insertion when a high priority DMA requires service and cannot wait
for the current chain to finish. This is supported only for SPORT DMA
channels. For more information, see Chapter 10, Serial Ports.
Fixed DMA Channel Arbitration
The shaded region in Table 2-28 (DMA channels 65 and 66) illustrates
that the priority shown is only valid if the IOD1 bus (external port DMA
channels) has a memory address block conflict with the IOD0 peripherals
bus. Otherwise, the IOD1 bus operates fully independently. Also note the
external port DMA channel changes priority, depending on the external
index addresses. If an external index address is assigned to an internal
index address, then DMA channel priority will change.
Table 2-28. DMA Channel 0–66 Priorities
DMA
Channel
Number
Peripheral
Group
Control/Status
Registers
Parameter
Registers
Data Buffer Description
IOD0 Peripheral Bus
0 (Highest
Priority
A SPCTL1,
SPMCTL1
IISP1A, IMSP1A,
CSP1A, CPSP1A
RXSP1A or
TXSP1A
Serial Port 1A Data
1 IISP1B, IMSP1B,
CSP1B, CPSP1B
RXSP1B or
TXSP1B
Serial Port 1B Data
2 SPCTL0,
SPMCTL0
IISP0A, IMSP0A,
CSP0A, CPSP0A
RXSP0A or
TXSP0A
Serial Port 0A Data
3 IISP0B, IMSP0B,
CSP0B, CPSP0B
RXSP0B or
TXSP0B
Serial Port 0B Data
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