ADSP-214xx SHARC Processor Hardware Reference 10-31
Serial Ports
• Word length (
SLEN, 8–32 bits)
• Channel Order (L_FIRST)
• Word Packing (PACK)
I
2
S mode is simply a subset of the left-justified mode. Note that in
I
2
S mode, the data is delayed by one SCLK cycle and the operation
transfer starts on the left channel first (L_FIRST = 1).
When both SPORT channels A and B are used in I
2
S/left-justified
mode with standard DMA enabled, then the DMA count should
be the same for both channels.
Figure 10-7 illustrates timing in I
2
S mode. In this example case, OPMODE =
1, LAFS = 1, and L_FIRST = 0.
Multichannel Mode
The processor’s serial ports offer a multichannel mode of operation, which
allows the SPORT to communicate in a time division multiplexed (TDM)
serial system. In multichannel communications, each data word of the
serial bit stream occupies a separate channel. Each word belongs to the
next consecutive channel. For example, a 24-word block of data contains
one word for each of the 24 channels.
Figure 10-7. Word Select Timing in I
2
S Mode
I
2
S MODE
SPORTx_DA/DB DATA
MSB
n
WORD n
LEFT CHANNEL
WORD n+1
RIGHT CHANNEL
LSB
n
MSB
n+1
WORD n
-
1
RIGHT CHANNEL
LSB
n
-
1
SPORTx_CLK
SPORTx_FS/WS
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