Analog Devices SHARC ADSP-214 Series User Manual

FIR Accelerator
6-34 ADSP-214xx SHARC Processor Hardware Reference
Processing Output
The accelerator uses all four MACs simultaneously to calculate one output
sample as shown in Figure 6-5 and the following procedure.
Figure 6-5. Multi-Iteration Filtering Flow
Load chain pointer and control registers
and enable accelerator
Load coefficients for
Perform all MACS
and calculate result
END
NO
NO
YES
the iteration
Prefill delay line
DMA partial sum
Is this the
last data for this
iteration?
Load next data
from output
buffer OR load 0 if
first iteration
Add partial sum
to the result
DMA Computed
result to output
Is this the
last iteration?
Raise channel
complete interrupt
YES
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Analog Devices SHARC ADSP-214 Series Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English