ADSP-214xx SHARC Processor Hardware Reference 15-29
Serial Peripheral Interface Ports
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
SPI Effect Latency
After the SPI registers are configured the effect latency is 2 PCLK cycles to
enable and 2 PCLK cycles to disable.
Programming Model
The section describes which sequences of software steps are required to get
the peripheral working successfully.
Changing SPI Configuration
Programs should take the following precautions when changing SPI
configurations.
• The SPI configuration must not be changed during a data transfer.
• Change the clock polarity only when no slaves are selected.
• Change the SPI configuration when
SPIEN = 0. For example, if
operating as a master in a multislave system, and there are slaves
that require different data or clock formats, then the master SPI
should be disabled, reconfigured, and then re-enabled.
However, when an SPI communication link consists of:
1. A single master and a single slave,
2. CPHASE = 1 and AUTOSDS = 0 for Master, CPHASE = 1 for slave
3. The slave’s slave select input is tied low
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