FIR Accelerator
6-40 ADSP-214xx SHARC Processor Hardware Reference
The input buffer size issmallest integer greater than or equal to
(N – 1 + W)/L for interpolation filters where:
• N is the number of taps
• W is the window size
• L is the interpolation ratio
To start the mode, programs configure the
FIR_RATIO and FIR_UPSAMP bits
(along with filter settings) in the FIRCTL2 register.
Channel Processing
Figure 6-6 on page 6-41 shows the flow diagram for processing a single
channel. Channels are processed in TDM format by setting the FIR_CH
bits greater one. In the time slot corresponding to a particular channel, the
corresponding TCB is loaded from internal memory.
1. The FIRCTL2 value is fetched from internal memory and is used to
configure the filter parameters for that channel.
2. The accelerator fetches the coefficients using the CIFIR register as
the pointer and loads them into coefficient memory.
3. The delay line is pre-filled using the IIFIR register as the pointer.
4. The accelerator calculates the first output and stores the result back
into the output buffer using the
OIFIR register as the pointer.
5. While calculating the output the accelerator fetches the next data
in parallel. After one window of data is processed, the index regis-
ters in the internal memory TCB ares updated so that in the next
time slot of the same channel, processing can be continued from
where it stopped.
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