DAI Signal Routing Unit Registers
A-128 ADSP-214xx SHARC Processor Hardware Reference
Frame Sync Routing Control Registers
(SRU_FSx, Group C)
The frame sync routing control registers (see Figure A-65 through
Figure A-69) route a frame sync or a word clock to the serial ports, the
SRC, the S/PDIF, and the IDP. Each frame sync input is connected to a
frame sync source based on the 5-bit values described in the group C
frame sync sources, (listed in Table A-77).
SPORTs 6 and 7 receive their frame syncs from other routed
sources but cannot route their own frame syncs to other SPORTs
or other peripherals internally through SRU. If externally needed,
they have to be routed through the DAI pins.
101100(0x2C) SPORT6_DA_O SPORT 6A Data
101101(0x2D) SPORT6_DB_O SPORT 6B Data
101110(0x2E) SPORT7_DA_O SPORT 7A Data
101111(0x2F) SPORT7_DB_O SPORT 7B Data
110000(0x30) DIT_O SPDIF TX BiphaseStream
110001(0x31)–111101(0x3D) Reserved
111110 (0x3E) LOW Logic Level Low (0)
111111 (0x3F) HIGH Logic Level High (1)
Table A-76. Group B Sources – Serial Data (Cont’d)
Selection Code Source Signal Description (Source Selection)
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