ADSP-214xx SHARC Processor Hardware Reference 6-13
FFT/FIR/IIR Hardware Modules
3. Third iteration:
a. Input coeff DMA from special coeff buffer[512] (offset =
1024)
b. Input DMA from special buffer[256] (offset = 512)
c. FFT computation
d. Output DMA to special buffer[256] (offset = 512)
4. Fourth iteration:
a. Input coeff DMA from special coeff buffer[512] (offset =
1536)
b. Input DMA from special buffer[256] (offset = 768)
c. FFT computation
d. Output DMA to special buffer[256] (offset = 768)
Horizontal FFT
1. Input coeff DMA from horizontal coeff buffer[32]
2. Input data DMA from special buffer[1024] (modifier = 2V, circbuf
= 2N)
3. FFT computation
4. Output DMA to Output Buffer[1024] (modifier = 2V,
circbuf = 2N)
This FFT generates a total of six partial FFT computations. Each compu-
tation has an input and output DMA which results in 12 interrupts.
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