ADSP-214xx SHARC Processor Hardware Reference 3-125
External Port
3. For a chained DMA, new TCB loading can be inhibited by clearing
the
CHEN bit while keeping all other control bits the same. The new
TCB is loaded once CHEN bit is re-enabled. The TCB load which
was happening when CHEN was cleared will complete.
4. Before initializing a chained DMA (including delay line) make sure
that the ICEP and ECEP registers are zero.
5. The DMA parameter registers (except DMACx) should not be written
to while chaining is occurring (the CHS bit is set), but any register
can be read during chaining.
6. A zero count for the ICEP, RCEP and TCEP registers is forbidden. If a
chain pointer with such a descriptor is programmed then the DMA
might hang. So a read count zero or a write count zero for a delay
line DMA is also forbidden.
AMI Initialization
After reset, the SDCLK is running with the default PLL settings. However,
the AMI must be configured and initialized. In order to set up the AMI,
use the following procedure. Note that the registers must be programmed
in order.
1. Chose a valid CCLK to SDCLK clock ratio in the PMCTL register.
2. Assign external banks to the AMI using the
EPCTL register (default).
3. Wait at least 8
PCLK cycles (effect latency).
4. Enable the global AMIEN bit and program the AMI control
(
AMICTLx) registers. (Define control settings for AMI based on
SDCLK speed and asynchronous memory specifications.
The
AMIMS and AMIS bits 1–0 of the AMI status register (AMISTAT) can be
checked to determine the current state of the AMI.
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