ADSP-214xx SHARC Processor Hardware Reference 9-11
Digital Application/Digital Peripheral Interfaces
Pin Buffers as Open Drain
For peripherals like the TWI and SPI (multi processing), the bus protocol
requires the pin drivers to work in open drain mode (Figure 9-6) for trans-
mit and receive operation. The signal input of the assigned pin buffer is
tied low. The peripheral's data output signal is connected to the
PBEN sig-
nal. In open drain mode, if PBEN = low, the level on the pin is depending
on the bus activities. If PBEN = high, the driver is conducting (input always
low level) and ties the bus low level. Note that for the SPI the ODP bit in
the SPICTL register must be enabled.
In open drain mode the data output signal is the peripheral’s
PBEN_O signal
DAI/DPI Pin Buffer Status
The signal levels on the DAI/DPI pins can be read with the
DAI/DPI_PIN_STAT registers. This allows conditions like for example:
Figure 9-6. Pin Buffer as Open Drain
IN
OUT
PIN
ENABLE
DAI_PBxx_I
DAI_PBxx_O
PBENxx_I
EXTERNAL DAI
PIN BUFFER
INTERFACE
TO SRU
PIN
BUFFER
PIN BUFFER
OUTPUT
PIN BUFFER
INPUT
(TIED LOW)
PIN BUFFER
ENABLE
TWI_DATA_PBEN_O
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