ADSP-214xx SHARC Processor Hardware Reference A-263
Registers Reference
FIFO Control Register (TWIFIFOCTL)
The TWI FIFO control register (
TWIFIFOCTL, shown in Figure A-151 and
described in Table A-142) affects only the FIFO and is not tied in any way
with master or slave mode operation.
Figure A-151. TWIFIFOCTL Register
Table A-142. TWIFIFOCTL Register Bit Descriptions (RW)
Bit Name Description
0 TWITXFLUSH Transmit Buffer Flush.
0 = Normal operation of the transmit buffer and its status bits
1 = Flush the contents of the transmit buffer and update the status
to indicate the buffer is empty. This state is held until this bit is
cleared. During an active transmit, the transmit buffer in this state
responds as if the transmit buffer is empty.
1 TWIRXFLUSH Receive Buffer Flush.
0 = Normal operation of the receive buffer and its status bits.
1 = Flush the contents of the receive buffer and update the status to
indicate the buffer is empty. This state is held until this bit is
cleared. During an active receive the receive buffer in this state
responds to the receive logic as if it is full.
2 TWITXINT2 Transmit Buffer Interrupt Length. Determines the rate at which
transmit buffer interrupts are generated. Interrupts may be gener-
ated with each byte transmitted or after two bytes are transmitted.
0 = An interrupt (TWITXINT) is set when TWITXS indicates one
or two bytes in the FIFO are empty (01 or 00).
1 = An interrupt (TWITXINT) is set when TWITXS indicates two
bytes in the FIFO are empty (00).
TWITXFLUSH
TWIRXFLUSH
TWIRXINT2
TWITXINT2
Receive Buffer Flush
Transmit Buffer Flush
Transmit Buffer Interrupt Length
Receive Buffer Interrupt Length
TWIBHD
Buffer Hang Disable
09 837564 2114 12 11 101315
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