ADSP-214xx SHARC Processor Hardware Reference 21-17
Two Wire Interface Controller
rupts. (By default, these interrupts are not configured in the
IRPTL
register—the PICRx register has to be programmed to configure them.)
This method shown in Listing 21-2 uses the PICR register with the code
value of the UARTx_RXI or UARTx_TXI interrupts.
Listing 21-2. Enabling TWI Interrupts
bit set mode1 IRPTEN; /* enables global interrupts */
bit set imask P1I; /* unmasks P1I interrupt */
ustat1=dm(PICR0); /* route TWII 0x17 to P1I */
bit set ustat1 P1I4|P1I2|P1I1|P1I0;
bit clr ustat1 P1I3;
dm(PICR0)=ustat1;
Interrupt Sources
The six different types of interrupts used by the TWI are grouped accord-
ing to master, slave or error operation. Those used in slave operation are:
• Transfer Initiate
• Transfer Complete
and for master operation:
• Transfer Complete
• TX/RX Buffer service
and for error operation:
• Transfer Error
• Transfer Overflow
For interrupt execution, the specific TWIRXINT receive bit or the specific
TWITXINT transmit bit must be enabled in the TWIIMASK register. The
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