ADSP-214xx SHARC Processor Hardware Reference I-29
Index
starting an interrupt driven transfer, 11-29,
11-30
status registers, DMA, 2-36
stopwatch function, RTC, 18-8
STROBEA (one shot frame sync A) bit,
14-13, A-195
STROBEB (one shot frame sync B) bit,
14-13, A-195
strobe period, 14-13
supervisory circuits, 23-41
support, technical or customer, -lxvi
switching from receive to transmit DMA,
15-35
synchronization with the external clock,
14-20
synchronizing frame sync output, 14-21
SYSCTL register
external port data pin mode select
(EPDATA) bits, A-6
interrupt request enable (IRQxEN) bits,
A-5
memory select (MSEN) bit, A-5
pulse width modulation select (PWMx)
bits, A-6
rotating priority bus arbitration (DCPR)
bit, 2-42
timer (flag) expired mode
(TMREXPEN) bit, A-5
SYSCTL (system control) register, A-4
system, 23-33
system control register. See SYSCTL
register
system design
baud rate, init value, 23-13
boot times, kernel, 23-22
bypass capacitors, 23-36
clock distribution, 23-33
conditioning input signals, 23-33
crosstalk, 23-37
decoupling capacitors, 23-36
system design (continued)
designing for high frequency operation,
23-33
generators, reset, 23-42
ground plane, 23-37
hold time, inputs, 23-36
input setup and hold time, 23-36
input signal conditioning, 23-33
kernel, boot, 23-22
latchup, 23-33
latency, input synchronization, 23-30
link port booting, 23-21
pin descriptions, 23-2
plane, ground, 23-37
PLL start-up, 22-3
power options, 22-6, 22-12
power supply, monitor and reset
generator, 23
-42
power-up, 22-3
recommendations and suggestions,
23-37
RESET
pin, 23-34
resetting the processor, 23-3
VCO encodings, 22-5
system interrupt, 9-32
T
TCB, 2-13 to 2-21, 2-32 to 2-35
TCB chain loading, 2-11
technical or customer support, -lxvi
technical support, -lxvi
test
loopback, SPI, A-236
test mode
DAI use in, 9-10, 9-40
data buffer use in, 2-11
loopback, SPI, 15-28, A-236
SPI, 4-21, 15-27
SPORT, 10-53, 10-60, 16-19, 18-11,
19-7, 21-18
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