ADSP-214xx SHARC Processor Hardware Reference 2-47
I/O Processor
Internal Transfer Completion
This mode of interrupt generation resembles the traditional SHARC
DMA interrupt generation. The interrupt is generated once the DMA
internal transfers are complete, independent of whether the DMA is a
transmit or receive. Therefore, for external transmit DMAs, when the
completion interrupt is generated there may still be an external access
pending at the external DMA interface.
The I/O processor only generates a DMA complete interrupt when
the channel’s count register decrements to zero as a result of actual
DMA transfers. Writing zero to a count register does not generate
the interrupt. To stop a DMA preemptively, write a one to the
count register. This causes one additional word to be transferred or
received, and an interrupt is then generated.
Access Completion
A DMA complete interrupt is generated when accesses are finished. For an
external write DMA, the DMA complete interrupt is generated only after
the external writes on the DMA external interface are complete. For an
external read DMA, the interrupt is generated when the internal DMA
writes are complete. In this mode the DMA interface can be disabled as
soon as the interrupt is received.
This mode is supported by the SPORT, SPI, link ports, and external port.
Core Single Word Transfer Interrupts
When a DMA channel’s buffer is not being used for a DMA process, the
core can generate an interrupt on single word transfers (writes or reads) of
the buffer of the respective peripheral. This interrupt service differs
slightly for each peripheral. In this case, the peripheral’s buffer generates
an interrupt when data becomes available at the receive buffer or when the
transmit buffer is not full (when there is room for the core to write to the
buffer). Generating interrupts in this manner lets programs implement
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