ADSP-214xx SHARC Processor Hardware Reference 3-7
External Port
External Port Arbitration
The external port arbiter is a key componant of the module. The arbiter
performs the following functions.
• Controls the speed for the AMI SDRAM/DDR2
• Controls the external banks individually
• Performs access arbitration for AMI, SDRAM/DDR2 and SPORT
access
• Allows channel freezing between core and DMA access to improve
fairness of bus ownership
Functional Description
The external port has four ports for communication:
• Peripheral core bus for control of external port IOP registers
• External port core bus for core access to external memory banks
• External port DMA bus for transfers between the external port and
internal memory.
• SPORT EP DMA bus for transfers between the external port and
the SPORTs.
Figure 3-1 shows a diagram of the external port for the ADSP-2147x and
ADSP-2148x processors (containing a SDRAM interface).
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