Interrupts
11-24 ADSP-214xx SHARC Processor Hardware Reference
DMA Interrupts
Using DMA transfer overrides the mechanism used for interrupt-driven
core reads from the FIFO. When the IDP_DMA_EN bit and at least one
IDP_DMA_ENx of the IDP_CTL1 register are set, the eighth interrupt
(IDP_FIFO_GTN_INT) in the DAI_IMASK_x registers is NOT generated.
At the end of the DMA transfer for individual channels, interrupts are
generated. These interrupts are generated after the last DMA data from a
particular channel has been transferred to memory. These interrupts
(IDP_DMAx_INT) are mapped from the bits 17–10 in the DAI_IMASK_x
registers and generate interrupts when they are set (= 1). These bits are
ORed and reflected in high level interrupts that are sent to the DAI
interrupt.
An interrupt is generated at the end of a DMA, which is cleared by read-
ing the DAI_IMASK_x registers.
FIFO Overflow Interrupts
If the data out of the FIFO (either through DMA or core reads) is not suf-
ficient to transfer at the combined data rate of all the channels, then a
FIFO overflow can occur. When this happens, new data is not accepted.
Additionally, data coming from the serial input channels (except for
32-bit I
2
S and left-justified modes) are not accepted in pairs, so that alter-
nate data from a channel is always from left and right channels. If overflow
occurs, an interrupt is generated if the
IDP_FIFO_OVR_INT bit in the
DAI_IMASK_x register is set (sticky bits in DAI_STAT0 register are also set).
Data is accepted again when space has been created in the FIFO.
Note that the total FIFO depth per channel is 9 locations: 1 location for
SIP to parallel data conversion + 8 locations for the IDP_FIFO.
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