ADSP-214xx SHARC Processor Hardware Reference 11-21
Input Data Port
Ping-Pong DMA
In ping-pong DMA, the parameters have two memory index values (index
A and index B), one count value and one modifier value. The DMA starts
the transfer with the memory indexed by A. When the transfer is com-
pleted as per the value in the count register, the DMA restarts with the
memory location indexed by B. The DMA restarts with index A after the
transfer to memory with index B is completed as per the count value.
The IDP DMA parameter registers have these functions:
• Internal index registers (
IDP_DMA_IxA, IDP_DMA_IxB). Index A/B
registers provide an internal memory address, acting as a pointer to
the next internal memory location where data is to be written.
• Internal modify registers (IDP_DMA_Mx). Modify registers provide
the signed increment by which the DMA controller post-modifies
the corresponding internal memory Index register after each DMA
write.
• Ping-Pong Count registers (IDP_DMA_PCx). Count registers indicate
the number of words remaining to be transferred to internal mem-
ory on the corresponding DMA channel.
This mode is activated when the IDP_EN bit, the IDP_DMA_EN bit, the
IDP_DMA_ENx bits, and the IDP_PINGx bits are set for a particular channel.
An interrupt is generated after every ping and pong DMA transfer (when
the count = 0).
Note that ping-pong DMA is repeated until stopped by resetting
the
IDP_DMA_ENx bits (OR global IDP_DMA_EN bit).
Multichannel DMA Operation
The SIP/PDAP can run both standard and ping-pong DMAs in different
channels. When running standard DMA, initialize the corresponding
IDP_DMA_Ix, IDP_DMA_Mx and IDP_DMA_Cx registers. When running
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