Clocking
4-4 ADSP-214xx SHARC Processor Hardware Reference
Status Registers (LSTATx). Programs can see several aspects of link port
operation using the status registers. These include bus status, buffer status,
receive and transmit status, and errors.
Clocking
The link port clock is derived from the clock out generator based on the
linkport to core clock ratio. For more information, see “Output Clock
Generator” on page 22-5.
The link port to core clock ratios (1:2, 1:2.5, 1:3, 1:4) can be programmed
in the PMCTL register. This programming is applicable only for the trans-
mitter. The receiver can operate at any asynchronous frequency up to the
maximum frequency, independent of the ratio programmed.
Functional Description
Each link port, shown in Figure 4-2, consists of eight data lines (LDATx7–0,
x = 0, 1), a link port clock line (LCLKx), and a link port acknowledge line
(LACKx). The LCLKx and LACKx pins of each link port allow handshaking for
asynchronous data communication between DSPs. Other devices that fol-
low the same protocol may also communicate with these link ports.
The link port operates in half-duplex mode, only receive or transmit oper-
ation can happen per linkport by using core or DMA. If full-duplex
operation is required both linkport must be used.
In receive operation, the data are received by the external receive buffer
packed into 32-bit format and shifted to the internal receive buffer. The
core or DMA read the data from the internal buffer. In transmit opera-
tion, the data are written to the internal transmit buffer moved to the
external transmit buffer to shift the data off-chip.The following sections
provide details on theis interface.
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