DDR2 DRAM Controller (ADSP-2146x)
3-60 ADSP-214xx SHARC Processor Hardware Reference
No Operation/Command Inhibit
The no operation (NOP) command to the DDR2 has no effect on opera-
tions currently in progress. When the controller is actively accessing the
DDR2 but needs to insert additional commands with no effect, the NOP
command is given.
The command inhibit command is the same as a NOP command, except
that the DDR2 is not chip-selected. When the controller is not accessing
any DDR2 external banks, the command inhibit command is given.
Address Mapping
To access DDR2, the DDR2 controller multiplexes the internal 32-bit
non-multiplexed address into three portions:
• Row address bits
• Column address bits
• Bank address bits
The non multiplexed address that is seen from the core/DMA is referred
to as IA31–0 in the following sections.
Address Translation Options
To provide flexible addressing, the DDR2ADDRMODE bit (bit 14) in the
DDR2CTL0 register is used to select the address mapping scheme—page
interleaving (default) or bank interleaving.
Page Interleaving Map
Programming the DDR2ADDRMODE bit to 0 selects the page interleaving
scheme. In this scheme consecutive pages fall in consecutive banks. The
bank address bits follow the most significant column address bits. This is
shown in Figure 3-14.
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