Programming Models
3-124 ADSP-214xx SHARC Processor Hardware Reference
interrupt is generated at the end of each delay line DMA block or at the
end of entire chained DMA, depending on the
PCI bit setting.
When delay line DMA is enabled with chaining, all the chained
DMA blocks follow the delay line DMA access procedure. It is not
possible to mix normal DMA with delay line DMA in chained
DMA.
Disabling and Re-enabling DMA
Use the following programming model to disable the external port DMA
during transfers.
1. Clear the DMAEN bit on the DMACx register.
2. Wait until the EXTS bit is 0.
3. Write 0x0 to the ICEP and DMACx registers. In cases where DMA is
used without chaining, writing to ICEP is not required.
4. Re-initialize the required DMA registers, and enable the DMACx reg-
ister while flushing the data/tap list FIFO.
Additional Information
1. If DMA is disabled in the middle of a data transfer, then DMA
interrupts cannot be relied on.
2. A single DMA (no chaining) can be stopped midway by clearing
the DMAEN bit in the DMACx register and then restarted from the
point where it was stopped by re-enabling the
DMAEN bit. This mode
of inhibiting the DMA only works with single DMA. If a
chained/delay line DMA is disabled by clearing
DMAEN bit then the
DMA should be reprogrammed again following the above pro-
gramming model.
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