Asynchronous Memory Interface
3-10 ADSP-214xx SHARC Processor Hardware Reference
(when all DMA engines are idle and no core or SPORT access to external
memory are pending).
Operating Mode
The following operation mode applies to the external port arbiter.
Arbitration Freezing
Arbitration length freezing can be used to improve the throughput of read
accesses by programming the various freeze bits of the EPCTL register.
When multiple DMA channels are reading data from SDRAM/DDR2
memory, channel freezing can improve the data throughput. By setting
the freeze bits (FRZDMA,FRZCR, and FRZSP), each channel request is frozen
for programmed accesses. For example, if the processor core is frozen for
32 accesses, and if the core requests 32 accesses to SDRAM/DDR2
sequentially, data throughput improves.
Freezing is based on the fact that sequential accesses to the
SDRAM/DDR2 provide better throughput then non-sequential accesses.
The arbiter also allows core or DMA access freeze which helps to balance
out system performance.
Channel freezing has no effect on write accesses.
Asynchronous Memory Interface
The asynchronous memory interface (AMI) is described in the following
sections.
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