ADSP-214xx SHARC Processor Hardware Reference 10-43
Serial Ports
When 16-bit received data is packed into 32-bit words and stored
in normal word space in processor internal memory, the 16-bit
words can be read or written with short word space addresses
Core Transfers
The following sections provide information on core driven data transfers.
Single Word Transfers
Individual data words may also be transmitted and received by the serial
ports, with interrupts occurring as each 32-bit word is transmitted or
received. When a serial port is enabled and DMA is disabled, the SPORT
interrupts are generated whenever a complete 32-bit word has been
received in the receive buffer, or whenever the transmit buffer is not full.
When performing core-driven transfers, write to the buffer designated by
the SPTRAN bit setting in the SPCTLx register. For DMA-driven transfers,
the serial port logic performs the data transfer from internal memory
to/from the appropriate buffer depending on the SPTRAN bit setting. If the
inactive SPORT data buffers are read or written to by core while the port
is being enabled, the core hangs. For example, if a SPORT is programmed
to be a transmitter, while at the same time the core reads from the receive
buffer of the same SPORT, the core hangs just as it would if it were
reading an empty buffer that is currently active. This locks up the core
until the SPORT is reset.
To avoid hanging the processor core, check the buffer’s full/empty status
when the processor core’s program reads a word from a serial port’s receive
buffer or writes a word to its transmit buffer. This condition can also hap-
pen to an external device, for example a host processor, when it is reading
or writing a serial port buffer. The full/empty status can be read in the
DXS
bits of the
SPCTLx register. Reading from an empty receive buffer or writ-
ing to a full transmit buffer causes the processor (or external device) to
hang, while it waits for the status to change.
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