ADSP-214xx SHARC Processor Hardware Reference 22-17
Power Management
bit set ustat2 PLLBP | PLLD4 |PLLM16; /* set a multiplier of
16 and a divider of 4 */
dm(PMCTL) = ustat2;
waiting_loop:
r0 = 4096; /* wait for PLL to lock at new rate
(requirement for VCO change) */
lcntr = r0, do pllwait until lce;
pllwait: nop;
ustat2 = dm(PMCTL); /* Reading the PMCTL register value
returns the DIVEN bit value as zero.
The DIVEN bit should be cleared while
taking the PLL out of bypass mode */
bit clr ustat2 PLLBP; /* take PLL out of Bypass,
PLL is now at new CCLK) */
dm(PMCTL) = ustat2;
bit set ustat2 DIVEN; /* Enable the divider */
dm(PMCTL) = ustat2;
lcntr = 15, do pllwait1 until lce;
pllwait1: nop;
Back to Back Bypass
Use this steps and the example shown in Listing 22-5 if the application
needs to re-enter the bypass mode.
1. Disable the bypass bit in the PMCTL register.
2. Wait 6 core clock cycles.
3. Enable the bypass bit.
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