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ADSP-214xx SHARC Processor Hardware Reference 3-79

External Port

Listing 3-6. EPDMA With Read Optimization

ustat1=dm(DDR2CTL0);

bit set ustat1 DDROPT|DDRMODIFY2;

dm(SDCTL)=ustat1;

nop;

r0=DFLSH;

dm(DMAC1)=r0;

r0=intmem; dm(IIEP1)=r0;

r0=2; dm(IMEP1)=r0;

r0=N; dm(ICEP1)=r0;

r0=2; dm(EMEP1)=r0;

r0=extmem; dm(EIEP1)=r0;

r0=DEN;

dm(DMAC1)=r0;

Notes on Read Optimization

The core and the DMA engine take advantage of the major improvements

during reads using read optimization. However, in situations where both

the core and DMA need to read from different internal memory banks

with different modifiers at the same time, programs need to choose

whether or not to use optimization. Note that from a throughput prospec-

tive, external port arbitration also is a factor. A good rule is that the

requester with the higher priority should have the same modifier as

DDR2MODIFY. In other words, if DMA has a higher priority over the core,

then the DMA modifier should match the

DDR2MODIFY setting.

Self-Refresh Mode

This mode causes refresh operations to be performed internally by the

DDR2, without any external control. This means that the SDC does not

generate any auto-refresh cycles while the DDR2 is in self-refresh mode.

Self-refresh entry—Self-refresh mode is enabled by writing a 1 to the

DDR2SRF bit of the DDR2 memory control register (DDR2CTL0). This deas-

serts the DDR2CKE pin and puts the DDR2 in self-refresh mode if no access

Analog Devices SHARC ADSP-214 Series User Manual

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