DDR2 DRAM Controller (ADSP-2146x)
3-82 ADSP-214xx SHARC Processor Hardware Reference
Additive Latency
Posted CAS operation is supported to make the command and data bus
efficient for sustainable bandwidths in DDR2 SDRAM. In this operation,
the DDR2 SDRAM allows a CAS read or write command to be issued
immediately after the RAS bank activate command (or any time during
the RAS-CAS-delay time, t
RCD
, period). The command is held for the
time of the additive latency (AL) before it is issued inside the device. The
read latency (RL) is controlled by the sum of AL and the CAS latency
(CL).
Therefore if a program wants to issue a read/write command before the
t
RCD
min, then AL (greater than 0) must be written into EMR(1). The write
latency (WL) is always defined as RL – 1 (read latency – 1) where read
latency is defined as the sum of additive latency plus CAS latency (RL =
AL + CL). Read or write operations using AL allow seamless bursts (refer
to seamless operation timing diagram examples in read burst and write
burst section). Note that the controller does support this feature, however
the performance is regardless of the AL settings written into EMR1.
Forcing DDR2 Commands
The DDR2C has some specific bits which can be used to aid in debug and
in specific system solutions.
Force Precharge All
Whenever an auto-refresh or a mode register set command is issued, the
internal banks are required to be in idle state. Setting bit 21 (=1) forces a
precharge all command to accomplish this. If the precharge all command
is not issued, the auto-refresh and mode register set commands can be ille-
gal depending on the current state.
Note that it is a good practice always to perform a force precharge all com-
mand before a forced refresh/mode register command.
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