ADSP-214xx SHARC Processor Hardware Reference A-123
Registers Reference
Serial Data Routing Registers (SRU_DATx, Group B)
The serial data routing control registers (see Figure A-58 through
Figure A-64) route serial data to the serial ports (A and B data channels)
and the input data port. Each of the data inputs specified are connected to
a data source based on the 6-bit values shown in Table A-76.
Figure A-58. SRU_DAT0 Register (RW)
Figure A-59. SRU_DAT1 Register (RW)
Serial Port 2 Data Channel A Input
SPORT2_DA_I (29–24)
Serial Port 1 Data
Channel A Input
SPORT1_DA_I (17–12) (con’t)
Serial Port 1 Data Channel B Input
SPORT1_DB_I (23–18)
Serial Port 0 Data Channel B Input
SPORT0_DB_I (11–6)
Serial Port 0 Data
Channel A Input
SPORT0_DA_I (5–0)
SPORT1_DA_I (17–12)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
Serial Port 4 Data Channel B Input
SPORT4_DB_I (29–24)
Serial Port 3 Data
Channel B Input
SPORT3_DB_I (17–12) (con’t)
Serial Port 4 Data Channel A Input
SPORT4_DA_I (23–18)
Serial Port 3 Data Channel A Input
SPORT3_DA_I (11–6)
Serial Port 2 Data
Channel B Input
SPORT2_DB_I (0–5)
SPORT3_DB_I (17–12)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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