ADSP-214xx SHARC Processor Hardware Reference 6-33
FFT/FIR/IIR Hardware Modules
Delay Line Memory
The accelerator has a 1024 TAP delay line to hold the data locally. The
DMA controller fetches the data from internal memory and loads it into
the delay line. Four read accesses can be made to the delay line
simultaneously.
Coefficient Memory
The accelerator has a 1024 deep coefficient memory to store the coeffi-
cients. The DMA controller loads the coefficients from internal memory
into coefficient memory. Four coefficients can be fetched from the coeffi-
cient memory simultaneously. If the soft filter length is more than 1024,
processing is done in multi-iteration mode.
Prefetch Data Buffer
This buffer is used to pre-fetch and keep the next input sample from the
memory (in parallel), when the compute unit is operating on the
delay-line corresponding to the current sample. The data pre-fetched in
this buffer is later used to update the delay line for the next sample. This
happens in parallel again, when the compute unit is not accessing the
delay line in other words when it is adding the output from the four
MACs and the partial sum register.
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