Features
2-2 ADSP-214xx SHARC Processor Hardware Reference
Features
I/O processor features are briefly described in the following list.
• Internal memory ↔ SPORT (DAI)
• SPORT (DAI) ↔ External Memory
• Internal memory ← IDP (DAI) unidirectional
• Internal memory ↔ SPI
• Internal memory ↔ Link port
• Internal memory ↔ MLB
• Internal memory ↔ UART
• Internal memory ↔ Accelerator
• Internal memory ↔ External memory (External port)
• Internal memory ↔ Internal memory (MTM, External port)
By managing DMA, the I/O processor frees the processor core, allowing it
to perform other operations while off-chip data I/O occurs as a back-
ground task. The multi-bank architecture of the ADSP-214xx internal
memory allows the core and IOP to simultaneously access the internal
memory if the accesses are to different memory banks. This means that
DMA transfers to internal memory do not impact core performance. The
processor core continues to perform computations without penalty.
To further increase off-chip I/O, multiple DMAs can occur at the same
time. The IOP accomplishes this by managing multiple DMAs of proces-
sor memory through the different peripherals. Each DMA is referred to as
a channel and each channel is configured independently.
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