Programming Model
21-20 ADSP-214xx SHARC Processor Hardware Reference
Slave Mode
When enabled, slave mode supports both receive and transmit data trans-
fers. It is not possible to enable only one data transfer direction and not
acknowledge (NAK) the other. This is reflected in the following setup.
1. Program the
TWISADDR register. The appropriate 7 bits are used in
determining a match during the address phase of the transfer.
2. Program the
TXTWI8 or TXTWI16 register. These are the initial data
values to be transmitted in the event the slave is addressed as a
transmitter. This is an optional step. If no data is written and the
slave is addressed and a transmit is required, the TWI_CLOCK is
stretched and an interrupt is generated.
3. Program the TWIFIFOCTL register. Indicate if transmit (or receive)
FIFO buffer interrupts should occur with each byte transmitted
(received) or with each 2 bytes transmitted (received).
4. Program the TWIIMASK register. Enable bits associated with the
desired interrupt sources. As an example, programming the value
0x000F results in an interrupt output to the processor when a valid
address match is detected, a valid slave transfer completes, a slave
transfer has an error, or a subsequent transfer has begun but the
previous transfer has not been serviced.
5. Program the TWISCTL register. This prepares and enables slave
mode operation. As an example, programming the value 0x0005
enables slave mode operation, requires 7-bit addressing, and indi-
cates that data in the transmit FIFO buffer is intended for slave
mode transmission.
Table 21-5 shows what the interaction between the TWI controller and
the processor might look like when the slave is addressed as a receiver.
To Next Page
Loading...
Need help?
General
