ADSP-214xx SHARC Processor Hardware Reference 6-31
FFT/FIR/IIR Hardware Modules
c. Four 32-bit floating-point and fixed-point multiplier and
adder units
d. One 32-bit buffer to efficiently supply data to the data path
e. One 32-bit buffer to hold previous partial sum
f. One 32-bit buffer to hold the output
2. Configuration registers for the number of TAPs, number of chan-
nels, filter enable, interrupt control, DMA enable, up sample/down
sample control, and ratios.
3. Core access interface for writing the DMA/filter configuration reg-
isters and reading the status register.
4. DMA bus interface for transferring data and/or coefficients to and
from the accelerator.
5. DMA configuration registers including chain pointer, input, out-
put, and coefficient registers.
Compute Block
The MAC unit, shown in Figure 6-4, has four multiply accumulators.
They operate simultaneously on a single filter as described below.
• The MAC unit operates on the data and coefficient fetched from
the data and coefficient RAMs.
• Each MAC can perform 32-bit floating-point or 32-bit fixed-point
MAC operations.
• Floating-point format is IEEE compliant.
• Multiply and accumulation operation (addition) are pipelined.
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