ADSP-214xx SHARC Processor Hardware Reference 10-29
Serial Ports
Master Serial Clock and Frame Sync Rates
The serial clock rate (
CLKDIV value) for internal clocks can be set using a
bit field in the DIVx register and the frame sync rate for internal frame sync
can be set using the FSDIV bit field in the DIVx register based on the MSTR
bit setting.
The transmitter sends the MSB of the next word in the same clock cycle as
the word select (SPORTx_FS) signal changes.
To transmit or receive words continuously in left-justified mode, load the
FSDIV register with SLEN–1. For example, for 8-bit data words set
FSDIV = 7.
Timing Control Bits
Several bits in the SPCTLx control register enable and configure left-justi-
fied mode operation:
• Master Mode Clock and Frame Sync (MSTR)
• Word Length (SLEN, 8–32 bits)
• Channel Order (L_FIRST)
• Word Packing (PACK)
Figure 10-6 illustrates only one possible combination of settings attainable
in the left-justified mode. In this example case,
OPMODE = 1, LAFS = 1, and
L_FIRST = 0. For complete descriptions of these bits, see “Serial Control
Registers (SPCTLx)” on page A-151.
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