Features
19-2 ADSP-214xx SHARC Processor Hardware Reference
Features
The following list provides a brief description of the watchdog timer’s
features.
• Programmable time out period – with about 1 second with 12
MHz clock.
• Time out resets the DSP and asserts the external reset (WDTRSTO
pin). DSP is reset internally to the chip upon WDT time out.
• WDT has its own clock (WDT_CLKIN) that is independent from the
SHARC CLKIN and any other clock derived from CLKIN.
• An internal oscillator to provide the clock input. This internal
oscillator provides a 2 MHz (typical frequency) clock.
• Status bit available for the processor to read which is cleared on
hardware reset assertion – it is not cleared on WDT generated
reset.
DMA Channels N/A
DMA Chaining N/A
Interrupt Source N/A
Boot Capable N/A
Local Memory N/A
Clock Operation WDTCLKIN
Table 19-1. Watchdog Timer Specifications (Cont’d)
Feature Availability
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