ADSP-214xx SHARC Processor Hardware Reference I-17
Index
MLB bits (continued)
next buffer start address (BEA), A-112
MLB registers
base, DMA, A-99
buffer, 8-5, 8-8, A-111 to A-113
channel control (MLB_CECRx), 8-7,
8-11, 8-13, 8-14, 8-16, A-102
channel interrupt status (MLB_CICR),
8-14, 8-15, A-99
channel status configuration
(MLB_CSCRx), 8-7, 8-12, 8-13,
8-14
device control and configuration
(MLB_DCCR), 8-4, 8-8, 8-16, A-94
status, channel (MLB_CSCRx), A-108
system data configuration
(MLB_SDCR), A-97
system mask configuration
(MLB_SMCR), 8-15, A-98
system status (MLB_SSCR), 8-4, 8-14,
8-15, 8-16, A-96
mode
left-justified (IDP), 11-6
left-justified (SPORT), 10-28, C-5
loopback (SPORT), A-170
right-justified (IDP), 11-6
serial mode settings (IDP), 11-17
single channel double frequency
(SPDIF), 13-12
standard serial, 10-25, C-2
TDM (SPORT), 10-3
timer, A-270
two channel (SPDIF), 13-12
mode fault error (MME) bit, 15-26, 15-27
mode fault (multimaster error) SPI DMA
status (MME)
bit, 15-26, 15-27
modes, audio, C-2 to C-9
MOSIx pins, 15-8, 15-14
most significant byte first (MSBF) bit,
A-234
MPEG-2 format, 13-17
MSBF (most significant byte first) bit,
A-234
MTxCCSx (serial port transmit compand)
registers, A-172
MTxCCSy and MRxCCSy (multichannel
compand select) registers, 10-12
MTxCSx (serial port transmit select)
registers, A-171
multibank operation with data packing,
3-36, 3-73
multichannel compand select (MTxCCSy
and MRxCCSy) registers, 10-12
multichannel filtering, FIR, 6-49
multichannel operation, 10-31
multiple processor system example, 3-39,
3-76
multiplexing
clockout enable (CLKOUTEN), A-11,
A-16
pins, 23-28 to 23-31
PWM pins, A-6
RESETOUT
, A-11, A-16
N
n greater than or equal to 512, repeat, 6-26
normal frame sync, 10-27
O
offset value, index registers, 2-27
one shot frame sync A or B (STROBEx)
bits, 14-13
one shot option (STROBEB) bit, 14-13
OPMODE (serial port operation mode)
bit, 10-25, 10-29
optimization
core read, 3-42, 3-78
DDR2 reads, 3-76 to 3-79
SDRAM reads, 3-40
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