Peripherals Routed Through the DAI
A-170 ADSP-214xx SHARC Processor Hardware Reference
Table A-88. SPMCTLx Register Bit Descriptions (RW)
Bit Name Description
0MCEAMultichannel Mode Enable, A Channels. Packed and multichannel A
modes only. One of two configuration bits that enable and disable
multichannel mode on serial port channels. See OPMODE bit (17).
0 = Disable multichannel A operation
1 = Enable multichannel A operation/packed mode
Note if MCEA bit is set, the corresponding SPEN_A bit in the SPCTL
register should be cleared.
4–1 MFD Multichannel Frame Delay. Set the interval, in number of serial clock
cycles, between the multichannel frame sync pulse and the first data
bit. These bits provide support for different types of T1 interface
devices. Valid values range from 0 to 15 with bits 4–1. Values of 1
to15 correspond to the number of intervening serial clock cycles. A
value of 0 corresponds to no delay. The multichannel frame sync pulse
is concurrent with first data bit.
11–5 NCH Number of Multichannel Slots (minus one). Select the number of
channel slots (maximum of 128) to use for multichannel operation.
Valid values for actual number of channel slots range from 1 to 128.
Use this formula to calculate the value for NCH:
NCH = Actual number of channel slots – 1.
12 SPL SPORT Loopback Mode. Enables if set (= 1) or disables if cleared (=
0) the channel loopback mode. Loopback mode enables debug capa-
bilities. Loopback works under the following SPORT configurations
where either of the two paired SPORTs can be set up to transmit or
receive, depending on their SPTRAN bit setting. Only the transmitter
acts as master to generate the clock and frame sync. The SPL bit
applies to all non multichannel modes.
SPORT0 and SPORT1. SPORT0 can only be paired with
SPORT1, controlled by the SPL bit in the SPMCTL0/1 registers.
SPORT2 and SPORT3. SPORT2 can only be paired with
SPORT3, controlled by the SPL bit in the SPMCTL2/3 registers.
SPORT4 and SPORT5. SPORT4 can only be paired with
SPORT5, controlled by the SPL bit in the SPMCTL4/5 registers.
SPORT6 and SPORT7. SPORT6 can only be paired with
SPORT7, controlled via SPL bit in the SPMCTL6/7 registers
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