Functional Description
10-18 ADSP-214xx SHARC Processor Hardware Reference
Serial Word Length
The serial word length is not unique and is based on the operation mode.
Moreover the companding feature limits the word length settings.
Words smaller than 32 bits are right-justified in the receive and transmit
buffers, residing in the least significant (LSB) bit positions (Table 10-4).
Internal Versus External Frame Syncs
Both transmit and receive frame syncs can be generated internally or input
from an external source. The
IFS/IMFS bit of the SPCTLx control register
determines the frame sync source.
When IFS/IMFS is set (=1), the corresponding frame sync signal is gener-
ated internally by the processor, and the SPORTx_FS signal is an output.
The frequency of the frame sync signal is determined by the value of the
frame sync divisor (
FSDIV) in the DIVx register.
When
IFS/IMFS is cleared (=0), the corresponding frame sync signal is
accepted as an input on the
SPORTx_FS signals, and the frame sync divisors
in the DIVx registers are ignored.
All frame sync options are available whether the signal is generated inter-
nally or externally.
Table 10-4. Data Length Versus Modes
Mode Word Length (SLEN) Bits
Standard Serial Mode 3–32
Left justified 8–32
I
2
S
8–32
Packed 3–32
Multichannel 3–32
To Next Page
Loading...
Need help?
General
