ADSP-214xx SHARC Processor Hardware Reference A-167
Registers Reference
SPORT Control 2 Registers (SPCTLNx)
These registers (where x signifies SPORT 0 through 7) allow programs to
set frame sync edge detection for I
2
S compatibility. These registers also
allow interrupts to be generated when transmit DMA count is expired or
when the last bit of last word is shifted out.
Note that these registers do not exist on previous SHARC proces-
sors (ADSP-212xx, ADSP-213xx).
Figure A-89. SPCTLNx Register
Table A-87. SPCTLNx Register Bit Descriptions (RW)
Bit Name Description
0I2SEFE I2S Extra Frame Edge. If set, SPORT generates the last LRCLK if
configured as I2S master (valid only for DMA). If cleared, (reset
value), behaves similar to previous SHARCs.
1 ETDINTEN External Transfer Done Interrupt. If set, interrupt occurs only after
the last bit of last word in the DMA is shifter out. If cleared, inter-
rupt occurs when the DMA counter expires. For chain pointer
DMA, if set, interrupt occurs:
1) only after that last word of last DMA block in the chain is shifted
out, if PCI=0.
2) When DMA counter expires for the initial DMA blocks (CP
nonzero) in the chain and the last bit of the last word is shifted out
for the last DMA block in the chain, if PCI=1.
For RX DMA, interrupt behaves in the same way independent of
the value of bit setting.
FSED
I2SEFE
I2S Extra Frame Edge
ETDINTEN
External Transfer Done
Interrupt
Frame S ync Edge
Detection
09 837564 2114 12 11 101315
COMPANDEN
Enable Companding on 1st
Active Channel
DISFSCNFLCT
Disable FS Underflow Error
DISTUVERR
Disable FS Conflict Error
DISFSWERR
Disable FS Error
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