ADSP-214xx SHARC Processor Hardware Reference 6-43
FFT/FIR/IIR Hardware Modules
Chain Pointer DMA
The DMA controller supports circular buffer chain pointer DMA. One
transfer control block (TCB) needs to be configured for each channel. The
TCB contains:
• A control register value to configure the filter parameters for each
channel
• DMA parameter register values for the input data (delay line)
• DMA parameter register values for coefficient load
• DMA parameter register values for output data
• Intermediate results in multi-iteration mode are saved in the out-
put buffer
As shown in “FIR Accelerator TCB” on page 2-16 and Figure 6-7, the
accelerator loads the TCB into its internal registers and uses these values
to fetch coefficients and data and to store results. After processing a win-
dow of data for any channel, the accelerator writes back the appropriate
values to the IIFIR and OIFIR fields of the TCB in memory, so that data
processing can begin from where it left off during the next time slot of
that channel.
The writeback value for input buffer is:
• IIFIR + W for single rate filtering.
• IIFIR + W × M for decimation (M = decimation ratio).
• IIFIR + W/L for interpolation (L = interpolation ratio).
• The writeback values for output buffer in floating point mode is:
OIFIR + W.
• The writeback values for output buffer in fixed point mode is:
OIFIR + 3 × W.
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