Programming Model
15-30 ADSP-214xx SHARC Processor Hardware Reference
Then the program can change the SPI configuration. In this case, the slave
is always selected. Data corruption can be avoided by enabling the slave
only after configuring both the master and slave devices.
Master Mode Transfers
For core or DMA transfers, when the SPI is configured as a master, the
ports should be configured and transfers started using the following steps:
1. Route all required signals (MOSI, MISO, SPICLK) for master mode
including the SPI_FLGx_O as slave select outputs.
2. Before enabling the SPI port, programs should specify which of
the slave-select signals (DPI pins) to use, setting one or more of the
required SPI flag select bits (DSxEN) in the SPIFLGx register. For
DMA operation set TIMOD = 10.
3. Set AUTOSDS bit to 1, to ensure the slave-selects are automatically
controlled by the SPI port. (When AUTOSDS = 0, only the CPHASE =
0 setting has automated control as with previous SHARC
processors)
4. Write to the SPICTLx register and set the SPIMS bit to enable the
device as a master. Configure the SPIBAUDx registers, and configur-
ing the appropriate word length, transfer format, baud rate, and
other necessary information.
The next steps are dependant on whether the access is a core or a DMA
access.
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